1. Field of the Invention
The present invention relates to a semiconductor integrated circuit formed with static memory (SRAM) circuits integrated on a semiconductor chip. More specifically, this invention relates to circuit configuration allowing for reduction of an operating voltage for a SRAM integrated circuit device.
2. Description of the Related Art
FIG. 33 shows a conventional type of a SRAM memory cell circuit. Symbols BL and BLB each indicates a bit line, WL a word line, Vdd a power line, and Vss a ground potential line. Further, reference numerals 111 and 112 denote a transfer transistor for access to a memory cell, 113 and 114 a driver transistor for driving a memory node for maintaining therein data for the memory cell, 115 and 116 a load transistor for supplying an electric charge for maintaining data in the memory cell, and 117 and 118 a storage node. Lowering a power voltage is the most simple and most effective method for reducing power consumption in a circuit. When a power voltage is low, however, a current in a transistor also drops, which disadvantageously causes such programs as lowering of an operating speed and degradation of operational stability.
Japanese Patent Laid-open No. 2000-114399 discloses the technique for raising a current, by connecting the back gates of a transfer transistor and a driver transistor in a SRAM memory cell and a gate, when the transistors are ON respectively. Japanese Patent Laid-open No. 2002-353340 discloses the technique for raising a current, by connecting the back gates of six transistors each constituting a SRAM memory cell and a gate, when the transistors are ON respectively. Further Japanese Patent Laid-open No. 11-16363 discloses the technique for raising a current in each of a driver transistor and a transfer transistor in a SRAM memory cell with a word line activated therein, by connecting back gates (or layers under a buried oxide film when an SOI (Silicon on Insulator) structure is used) of the transfer transistor and the driver transistor for the memory cell to a word line.
Representative examples of the pass transistor logic circuit described in Embodiment 12 are described in “PRINCIPLE OF CMOS VLSI DESIGN, A System Perspective” by Neil H. E. Weste and Kamran Eshraghin, SECOND EDITION, p. 304-307.